New materials and material compositions are being employed in industry in order to improve semiconductor devices such as transistors, for example. This allows to improve the processing speed and performance of integrated circuits (ICs).
A typical example is the deployment of Silicon-Germanium (SiGe) on Silicon. An example of a well-known SiGe heterostructure device 10 is illustrated in FIG. 1. The device 10 comprises a (001)-oriented silicon substrate 11. A graded SiGe-layer 12 is situated on top of the Si substrate 11. The layer 12 allows for a gradual modification of the lattice constant starting from the silicon's lattice constant to a constant that is mainly determined by the concentration of the Ge in the SiGe-layer 12. In the given example, a constant composition buffer layer 13 is formed on top of the graded SiGe-layer 12. The SiGe-layer 12 together with the buffer layer 13 serve as a virtual substrate for the layers that are formed in subsequent process steps. A stack of active device layers 14 is formed on the virtual substrate. The concentration of Ge is depicted in the graph 15 on the left hand side of the device 10. The Ge concentration (x) in the SiGe-layer 12 is gradually increased from x=0 to x=xf. The layer 12 is typically several microns thick in order to ensure that the defect concentration is low.
There are several widely used processes for making such SiGe devices 10. Molecular beam epitaxy (MBE) and ultra-high vacuum chemical vapor deposition (UHV-CVD) are just two examples. Using these processes the fabrication of Ge-rich SiGe structures and devices is difficult. It is another disadvantage of the known approaches that the growth rate is low. Since a certain minimum thickness of the SiGe-layer 12 is required to guarantee an acceptable level of the defect concentration, the formation of this layer takes quite some time. This is, however, highly unfavorable for industrial mass production.
There are two different UHV-CVD processes. The first one is called hot-wall UHV-CVD and the second one is called cold-wall UHV-CVD or rapid thermal CVD (RTCVD).
Hot-wall CVD is well suited for batch processing and is carried out at low, typically between 450° and 550° C., substrate temperatures. Strained Si-channels on SiGe-buffers can be made using hot-wall UHV-CVD. Very high electron mobilities of more than 105 cm2/Vs have been reported by is mail et al. in “Extremely high electron mobilities in Si/SiGe modulation-doped heterostructures”, Appl. Phys. Lett, Vol. 66, p. 1077, 1995. The hot-wall UHV-CVD has several disadvantages, such as                low growth rate on the order of about nm/min at substrate temperatures around 550° C. for pure Si, as reported by B. S. Meyerson et al. in “Cooperative growth phenomena in silicon/germanium low-temperature epitaxy”, Appl. Phys. Lett., Vol. 53, p. 2555, 1988;        large surface roughness caused by so-called cross-hatch due to relaxation. The cross-hatch effect is more prominent the steeper the gradient of concentration (grading rate) is. The difference in altitude between hills and grooves is typically about 30 nm even at the surface of a buffer layer with a comparatively low Ge concentration of xf=0.3 at the surface. The surface roughness has a detrimental effect on the quality of MODFETs, as described by M. Arafa et al. in “Device and fabrication issues of high performance Si/SiGe Fets”, Nat. Sci. Soc., Symp. Proc. Vol. 533, p. 83, 1998.        The hot-wall process is difficult to control in particular at high Ge-concentrations, as described by P. M. Mooney et al. in “SiGe technology: heteroepitaxy and high-speed microelectronics”, Annu. Rev. Mater. Sci., Vol. 30, pp. 335, 2000. The hot-wall process is thus not suited for high mobility hole transport. High performance p-MODFETs with pure Ge channels thus cannot be made using the hot-wall technique.        
Cold-wall CVD is suited for processing single wafers. This process is typically carried out at temperatures above 700° C. First results concerning graded SiGe buffer layers can be found in a paper written by E. A. Fitzgerald et al., entitled “Totally relaxed GexSix-1 layers with low threading dislocation densities grown on Si substrates”, Appl. Phys. Lett., Vol. 59, p. 811, 1991. At substrate temperatures between 800° and 900° C. the surface roughness is even greater than the surface roughness of layers made by the hot-wall process. An RMS-roughness of 30 nm at a Si0.7Ge0.3-buffer has been reported with a tendency to an even stronger surface roughness when the Ge-concentration in the buffer layer is increased. Details are given in “Novel dislocation structure and surface morphology effects in relaxed Ge/Si—Ge(graded)/Si structures”, S. B. Samavedan et al., J. Appl. Phys, Vol. 81, p. 3108, 1997.
A SiGe buffer where the concentration is graded such that 100% Ge is obtained at the buffer layer's surface are very rough, when made using cold-wall UHV-CVD (RMS-roughness greater than 30 nm). Heterostructure devices cannot be formed on these rough surfaces without applying a chemical-mechanical polishing (CMP) process. For details refer to “Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing”, E. A. Fitzgerald et al., Appl. Phys. Lett, Vol. 72, p. 1718, 1998.
Until now, no MODFET structures and high-mobility hole transport devices have been made and reported using cold-wall UHV-CVD for the entire layer stack.
Another well-known process technology is called low-pressure chemical vapor deposition (LPCVD). As reported by A. C. Churchill et al. in “High-mobility two-dimensional electron gases in Si/SiGe heterostructures on relaxed SiGe layers grown at high temperature” Semicond. Sci. Technol., Vol. 12, p. 943, 1998, the relatively high process temperatures in an LPCVD process also lead to a remarkable surface roughness. This is even the case at a grading rate of less than 10%/μm. At a Ge-concentration of xf=0.24 at the buffer surface and a substrate temperature of 800° C., an RMS-roughness of up to 6 nm was reported. For details see “Mosaic crystal tilts and their relationship to dislocation structure, surface roughness and growth conditions in relaxed SiGe layers”, by D. J. Wallis et al., Mat. Res. Soc. Symp. Proc., 533, p. 77, 1998.
A graded buffer layer with a Ge-concentration of 100% (i.e., xf=1) at the surface shows an even larger roughness with an RMS of 160 nm.
LPCVD, like cold-wall UHV-CVD, is not suited for making structures that require a high hole mobility.
As mentioned above, MBE is another process that is widely used for making semiconductor structures. A virtual substrate (layers 12 and 13 in FIG. 1) can be made using an MBE process without facing serious problems. Since the chemical composition of the layers is to a large extent independent of the substrate temperature, the relaxation and surface roughness of the virtual substrate layer can be optimized by choosing an appropriate temperature profile and grading rate, as addressed by J.-H. Li et al. in “Strain relaxation and surface morphology of compositionally graded Si/Si1-xGex buffers”, J. Vac. Sci. Technol., Vol. B 16, p. 1610, 1998 and in E. A. Fitzgerald et al., APL, Vol. 59, p. 811, 1991.
The most serious disadvantage of MBE is the limited capacity of the evaporation crucibles. This is a disadvantage in particular when growing thick SiGe-buffer layers, as described by T. Hackbarth et al. in “Alternatives to thick MBE-grown relaxed SiGe buffers”, Thin Solid Films, Vol. 369, p. 148, 2000. MBE is thus not well suited for an industrial production of SiGe devices.
For devices with Ge-rich compressively strained channels on a virtual substrate, there is a tendency for a three-dimensional growth. In particular pure Ge-layers show a remarkable surface roughness, except when the layers are grown at low substrate temperature around 300° C. At such low temperatures, however, the electrical properties of the devices are not acceptable anymore.
It is an object of the present invention to provide a method for making improved SiGe structures, such as MODFET structures or MODQW structures.
It is an object of the present invention to provide a method for making SiGe devices with improved hole conductivity.
It is an object of the present invention to provide improved SiGe heterostructure devices.
It is an object of the present invention to provide a growth system for carrying out a method for making SiGe devices.